Buck Converter Calculator

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Introduction to buck converter power-stage calculations

A buck converter changes a higher DC input into a lower regulated output by switching the input and smoothing the resulting waveform with an inductor and capacitor. This calculator estimates the steady-state duty cycle, switching times, inductor ripple, peak and valley current, continuous or discontinuous conduction mode, diode loss, and output ripple. It also suggests preferred E12 component values for a conventional first-pass design.

The ideal starting point is $D = \frac{V_{out}}{V_{in}}$ . Real hardware needs more on-time because the high-side switch and freewheeling device lose voltage. The calculator therefore shows the ideal ratio for reference and a drop-corrected result for practical design. It also tests whether the entered load is high enough to keep the inductor current above zero.

A useful buck calculation is an operating-point estimate rather than a complete converter design. Input voltage can change with battery state, adapter tolerance, cable loss, or an upstream supply. Load current can range from standby demand to a short transient peak. Inductance, capacitance, diode drop, MOSFET resistance, and switching frequency all have tolerances. For that reason, the most informative approach is to repeat the calculation at the corners that matter: maximum input for ripple and minimum on-time, minimum input for duty-cycle headroom, maximum load for current stress, and minimum load for the CCM-to-DCM transition.

The calculator treats the power stage as a steady-state switched network. During the high-side interval, the source applies positive voltage across the inductor and its current rises. During the freewheeling interval, the inductor continues delivering energy to the load while its current falls. The output capacitor accepts the alternating part of that current so the load sees a comparatively smooth voltage. These relationships are simple enough for a first-pass calculation, but they reveal several design constraints that an ideal voltage-ratio calculation alone would miss.

Formulas for buck duty cycle, ripple and conduction mode

For ideal components, inductor volt-second balance gives:

D = \frac{V_{out}}{V_{in}}

Here $D$ is duty cycle, $V_{out}$ is output voltage, and $V_{in}$ is input voltage. Including the switch drop $V_{SW}$ and diode drop $V_{D}$ gives this balance:

D (V_{in} - V_{SW} - V_{out}) + (1 - D) (- V_{D} - V_{out}) = 0

Solving for $D$ produces the calculator’s primary duty-cycle result:

D = \frac{V_{out} + V_{D}}{V_{in} - V_{SW} + V_{D}}

The diode drop appears in both the numerator and denominator because the diode conducts only during $1 - D$ of the period. For a synchronous buck, the low-side MOSFET’s approximate conduction drop may be entered in place of $V_{D}$ . An alternative efficiency-based estimate is:

D = \frac{V_{out}}{V_{in} \cdot η}

Efficiency and explicit device drops model overlapping losses, so compare the two estimates rather than multiplying them together. A single efficiency number includes conduction, switching, magnetic, controller, and other losses in an aggregate way. Explicit drops model only part of that loss picture, but they preserve the inductor volt-second relationship needed for current-ripple calculations. Neither method should be mistaken for a detailed loss simulation.

The switching period is the reciprocal of switching frequency:

T_{s} = \frac{1}{f_{sw}}

The on-time is the duty cycle multiplied by this period, and the remaining part is the off-time. Those timing results are important because every controller imposes practical limits. At high input voltage, the required pulse may become shorter than the controller’s minimum on-time. Near dropout, the controller may reach its maximum duty cycle or minimum off-time before it can maintain the requested output.

The peak-to-peak inductor current ripple is calculated from the on-interval:

{ΔI}_{L} = \frac{(V_{in} - V_{SW} - V_{out}) \cdot D}{L \cdot f_{sw}}

Here $f_{sw}$ is switching frequency and $L$ is inductance. The equivalent off-interval check is:

{ΔI}_{L} = \frac{(V_{out} + V_{D}) \cdot (1 - D)}{L \cdot f_{sw}}

With ideal devices this reduces to ${ΔI}_{L} = \frac{(V_{in} - V_{out}) D}{f_{s} L}$ . A common design target is:

{ΔI}_{L} = (0.2 to 0.4) \cdot I_{out (\max)}

Rearranging for inductance gives:

L = \frac{V_{out} \cdot (V_{in} - V_{out})}{{ΔI}_{L} \cdot f_{sw} \cdot V_{in}}

The 20–40% range is a design convention, not a hard electrical limit. A larger inductor lowers ripple and peak current, can reduce output ripple, and keeps the converter in continuous conduction down to a lighter load. The tradeoffs are physical size, winding resistance, cost, and potentially slower current response. A smaller inductor responds quickly and may reduce size, but it raises peak current, RMS stress, core loss, and the amount of alternating current that the output capacitor must handle.

Use the effective inductance at the intended DC bias. The value printed on an inductor is often measured at a small test signal with little or no DC current. Powdered-iron, ferrite, and molded composite parts can lose a meaningful percentage of inductance as current rises. If a nominal 22 µH component falls to 15 µH at operating current, actual ripple is about 47% higher than a calculation based on 22 µH. Temperature and manufacturing tolerance can reduce the value further.

Peak current and the CCM/DCM boundary

In continuous conduction, the load current lies at the center of the triangular ripple. Peak switch and inductor current are therefore:

I_{SW (\max)} = I_{out} + \frac{{ΔI}_{L}}{2}

The corresponding valley-current relationship is:

I_{valley} = I_{out} - \frac{{ΔI}_{L}}{2}

The mode boundary occurs when the valley reaches zero:

I_{out} > \frac{{ΔI}_{L}}{2} (CCM), I_{out} < \frac{{ΔI}_{L}}{2} (DCM)

The corresponding critical inductance is $L_{crit} = \frac{(V_{out} + V_{D}) (1 - D)}{2 f_{sw} I_{out}}$ .

For the ideal DCM model, let $M = V_{out} / V_{in}$ , $K = 2 L / (R T_{s})$ , and $R = V_{out} / I_{out}$ . DCM occurs when $K < K_{crit} = 1 - D$ , with:

D_{DCM} = M \sqrt{\frac{K}{1 - M}}, K = \frac{2 L f_{sw} I_{out}}{V_{out}}

The calculator retains the explicit drops in its DCM solution. The inductor current forms a triangle with peak $I_{pk}$ spanning $D + D_{2}$ . When $V_{D} = V_{SW} = 0$ , the corrected expression reduces to the ideal result:

D_{DCM} = \sqrt{\frac{2 I_{out} L f_{sw} (V_{out} + V_{D})}{(V_{in} - V_{SW} - V_{out}) (V_{in} - V_{SW} + V_{D})}}

The diode interval is $D_{2} = D (V_{in} - V_{SW} - V_{out}) / (V_{out} + V_{D})$ ; $D_{3}$ is the remaining zero-current interval. Average diode current in DCM is $0.5 I_{pk} D_{2}$ , rather than the CCM value $I_{out} (1 - D)$ .

DCM is not automatically a fault. Many controllers intentionally enter diode-emulation, pulse-skipping, burst, or variable-frequency modes at light load to improve efficiency and prevent reverse current. The displayed DCM estimate describes the basic energy-transfer geometry for a constant-frequency cycle; an actual controller may use a different control law. Consult its data sheet before using the DCM duty cycle to predict light-load behavior, output ripple, audible noise, or switching frequency.

The calculated peak current is a normal steady-state value, not a complete current-limit recommendation. Startup, load steps, short circuits, slope compensation, current-sense tolerance, and control-loop overshoot can all create higher current. Inductor saturation current and semiconductor pulse-current ratings should therefore exceed the calculated peak with appropriate margin. Also check RMS current because copper and MOSFET conduction losses depend more closely on RMS current than on average load current.

Capacitance and ESR contributions to output ripple

The ideal capacitive ripple estimate is:

{ΔV}_{out (C)} = \frac{{ΔI}_{L}}{8 \cdot f_{sw} \cdot C_{out}}

Capacitor ESR adds:

{ΔV}_{out (ESR)} = ESR \cdot {ΔI}_{L}

The calculator adds these terms conservatively. In many electrolytic-capacitor designs, ESR dominates. Diode average current and conduction loss are estimated with $I_{F} = I_{out (\max)} \cdot (1 - D)$ and $P_{D} = I_{F} \cdot V_{F}$ .

If a designer allocates a specific ripple budget to ESR, the corresponding first-pass ESR ceiling is:

{ESR}_{\max} = \frac{{ΔV}_{ESR (allowed)}}{{ΔI}_{L}}

Capacitor selection requires more than meeting a nominal capacitance. Ceramic capacitors can lose much of their rated capacitance under DC bias, especially when a small case size carries a voltage near its rating. Electrolytic and polymer capacitors have frequency- and temperature-dependent ESR. Every capacitor also has an allowable ripple-current rating, and the PCB contributes parasitic resistance and inductance. Enter effective values at the operating voltage and switching frequency whenever the manufacturer supplies suitable curves.

The two ripple terms do not always peak at exactly the same instant in a detailed waveform, so simple addition is intentionally conservative. High-frequency spikes caused by switch-node ringing, diode recovery, package inductance, and layout are not represented by either term. Those spikes often dominate an oscilloscope trace if the probing loop is large. For meaningful bench verification, use a ground spring or coaxial tip-and-barrel method directly across the output capacitor.

How to use this buck converter calculator

Enter the input voltage at the operating condition you want to test. Maximum input is usually most useful for ripple and peak-current checks. Output voltage must be positive and lower than input voltage. Output current is the DC load at the selected operating point; use a light-load value when checking the transition into DCM.

Enter inductance and switching frequency with their unit selectors. Output capacitance and ESR are optional, but both are needed for a useful real-world ripple estimate. The optional diode and switch drops improve the volt-second model. For a synchronous converter, use an approximate low-side FET conduction drop in the diode field. The optional efficiency value generates a separate comparison duty cycle.

Select Calculate power stage to update the results, load sweep and waveform. The load sweep shows where the current changes between CCM and DCM. Copy summary creates a text report, while Download sweep CSV exports the numerical sweep. Reset restores the example values.

Choose input corners deliberately. Maximum input usually creates the greatest inductor charging voltage and can produce the shortest on-time. Minimum input usually demands the highest duty cycle and can expose dropout. If the source is a battery, include its fully charged voltage, discharged voltage, wiring resistance, and any load-dependent sag. If the source is another converter, include regulation tolerance and transient overshoot rather than entering only the nominal label value.

For output current, calculate at both the sustained maximum and representative light loads. Maximum load is important for inductor peak current, semiconductor stress, conduction loss, and thermal design. Light load reveals whether the current reaches zero. A converter that operates in CCM at full load can enter DCM well before standby. The load sweep is useful for seeing that transition, but it does not replace the controller’s documented mode behavior.

For diode drop, use a forward-voltage estimate at an appropriate current and temperature. A Schottky diode’s drop is not constant, and its leakage can rise sharply when hot. In a synchronous buck, estimate the low-side MOSFET drop from current multiplied by on-resistance, allowing for the higher resistance at operating junction temperature. Apply a similar method to the high-side switch field. Because current changes throughout the cycle, these constant-drop entries remain approximations.

Use the efficiency field only as a comparison when you have a measured or data-sheet efficiency estimate near the intended operating point. Efficiency varies with input voltage, output current, switching frequency, and temperature. The efficiency-based duty result is not used to generate the inductor waveform because a lumped loss percentage does not identify how much voltage appears across the inductor during each switching state.

Worked example: a 12 V to 3.3 V rail at 2 A

Consider $V_{in} = 12$ V, $V_{out} = 3.3$ V, $I_{out} = 2$ A, $L = 22$ µH and $f_{sw} = 300$ kHz. Add a 0.4 V diode drop, 0.2 V switch drop, 470 µF capacitor and 80 mΩ ESR.

The ideal duty cycle is 27.50%, while the drop-corrected result is about 30.33%. Inductor ripple is approximately 0.391 A peak-to-peak, so peak current is about 2.20 A and valley current is about 1.80 A. The 0.195 A CCM boundary is far below the 2 A load.

The ideal capacitive ripple is only about 0.35 mV, but the ESR contribution is about 31.2 mV. This contrast explains why nominal capacitance alone cannot predict output ripple. The calculated diode loss is also substantial enough to make synchronous rectification worth evaluating.

The example should next be checked at the real input limits. Raising the input tends to increase the inductor’s charging slope and may shorten the required pulse. Reducing input voltage moves duty cycle upward and can bring the converter closer to dropout. At each corner, compare peak current against the controller limit and the inductor’s bias-dependent saturation curve. The normal 2.20 A peak does not justify choosing a component rated at exactly 2.20 A; tolerances and transient demand require margin.

Now consider light load. With the same inductance and switching frequency, the CCM boundary is about 0.195 A. At loads below that value, a fixed-frequency diode buck cannot sustain a positive valley current, so the basic DCM model applies. A synchronous controller may instead permit reverse current, disable the low-side switch at zero current, skip pulses, or enter a proprietary low-power mode. The calculator identifies the energy-balance boundary, while the controller data sheet determines what the hardware actually does after crossing it.

The output power at this operating point can be summarized by:

P_{out} = V_{out} \cdot I_{out}

For 3.3 V at 2 A, the load receives 6.6 W. Total input power will be higher because the diode, switches, inductor, capacitor, gate driver, and controller dissipate energy. The calculator’s diode estimate covers only forward conduction. It does not include reverse leakage, reverse recovery, MOSFET switching loss, inductor copper loss, core loss, or controller consumption, so it should not be treated as a complete efficiency prediction.

Interpreting buck converter results and component ratings

Compare calculated on-time with the controller’s minimum on-time and the duty cycle with its maximum-duty specification. Rate the inductor for peak current with margin and check its inductance under DC bias, not only its nameplate value. The switch current limit must also exceed the calculated peak during normal operation and transients.

A ripple ratio near 20–40% is conventional, but it is not a universal requirement. Lower ripple can reduce peak current and delay DCM at the cost of a larger inductor. Higher ripple allows smaller inductance but increases peak current, core loss and output ripple. If ESR dominates the voltage ripple, adding capacitance alone may accomplish little; lower-ESR parts or parallel capacitors are more effective.

Interpret the suggested E12 values as convenient starting points. The inductance recommendation targets 30% ripple using an idealized expression, while the capacitance recommendation targets a 1% capacitive ripple term and excludes ESR. A preferred nominal value must still be checked after tolerance, temperature, aging, and DC-bias derating. The nearest catalog value may also have unsuitable saturation current, winding resistance, package size, or thermal performance.

Inductor saturation and thermal current are different ratings. Saturation current describes the current at which inductance falls by a specified percentage, and manufacturers do not all use the same percentage. Thermal current describes a specified temperature rise under test conditions. A part can meet one rating and fail the other. Compare the calculated peak with saturation behavior and compare RMS current with thermal performance, then account for the poorer cooling commonly found on a compact PCB.

For the high-side MOSFET, voltage rating must exceed the input plus switching overshoot. Current rating alone is rarely the limiting specification because on-resistance, gate charge, package thermal resistance, and safe operating conditions interact. The low-side MOSFET or diode must tolerate the same switch-node transients. A diode also needs adequate average current, surge current, reverse-voltage, leakage, and thermal ratings. Synchronous rectification reduces forward loss but introduces dead-time and shoot-through design concerns.

Output-capacitor ripple current, voltage rating, effective capacitance, ESR, and control-loop requirements all matter. Some regulator control methods require an ESR range or depend on a particular output pole and zero. Replacing an electrolytic capacitor with a very low-ESR ceramic bank can destabilize an older controller even though the simple ripple estimate improves. Always compare the selected network with the controller manufacturer’s compensation guidance and recommended component range.

The load-sweep CSV is useful for design review because it records how mode, duty cycle, ripple ratio, peak current, and estimated output ripple change with load. However, its rows reuse the same entered component values and constant drops. They do not model temperature rise, nonlinear semiconductor curves, pulse skipping, changing frequency, or bias-dependent inductance. Treat the sweep as a map of the simplified model rather than a replacement for electrical simulation.

Practical buck converter checks beyond the calculator

A reliable design process continues from calculation into controller-limit review, loss estimation, simulation, layout, and measurement. Start by checking the regulator’s absolute maximum ratings and recommended operating limits. Verify input voltage, output range, switching frequency, current-sense range, duty-cycle limits, minimum controllable on-time, minimum off-time, soft-start behavior, and supported output capacitance. Absolute maximum ratings are survival boundaries, not desirable operating points.

Next estimate losses at the important corners. High-side and low-side conduction loss depend on RMS current and temperature-adjusted resistance. Switching loss depends on voltage, current, transition time, frequency, gate drive, and device capacitances. Diode reverse recovery can add stress even in a synchronous design because the body diode may conduct during dead time. Inductor loss includes DC winding resistance, skin and proximity effects, and frequency-dependent core loss. These losses feed back through temperature, increasing resistance and sometimes changing magnetic behavior.

PCB layout is part of the power stage. Keep the high-current input loop formed by the input capacitor, high-side switch, low-side switch or diode, and ground compact. Place the ceramic input bypass close to the switching devices. Keep the switch-node copper no larger than necessary because it is a strong source of electric-field noise. Route feedback away from the switch node and sense the output at a quiet point. Use an appropriate ground strategy and short gate-drive paths.

Transient performance needs a control-loop model or measurement. The steady-state capacitor ripple formula does not predict the voltage deviation caused by a sudden load step. During a rapid increase in demand, the output capacitor supplies the current difference until the inductor current and control loop respond. Capacitance, ESR, control bandwidth, current limit, and slew rate all affect the excursion. During load release, stored inductor energy can push the output upward. These events often set capacitor and current-limit requirements more strongly than steady-state ripple.

Bench validation should include startup, shutdown, no load, minimum load, maximum load, input extremes, load steps, line steps, and fault recovery. Measure switch-node voltage, inductor current when practical, output ripple, efficiency, and component temperatures. Use probes and bandwidth limits appropriate to the question being asked. A long oscilloscope ground lead can display ringing that belongs mainly to the probe loop, while excessive bandwidth can obscure the lower-frequency ripple of interest.

Assumptions behind these buck converter estimates

The duty and ripple equations assume periodic steady state, a constant switching frequency, a regulated output, and approximately constant component values during each calculation. Input and output voltages are treated as DC values. The inductor current is modeled as piecewise linear because each switching state applies an approximately constant voltage across the inductor. Capacitor current is derived from that idealized inductor waveform.

The explicit switch and diode entries are constant voltage drops. Real MOSFET drops vary with current and junction temperature, while diode forward voltage varies with current, temperature, and device technology. Dead time, body-diode conduction, switch transition intervals, wiring resistance, and inductor winding resistance alter volt-second balance but are not explicitly included. The drop-corrected duty result is consequently more practical than the ideal ratio without being a transistor-level solution.

The CCM test assumes the triangular ripple predicted by the steady-state CCM equations. At the boundary, small changes in load, inductance, frequency, or control strategy can change mode. Some controllers enforce forced CCM and permit negative inductor current. Others use zero-current detection to prevent reversal. Hysteretic, constant-on-time, pulse-frequency, and burst-mode controllers may not follow the fixed-frequency DCM waveform shown by this tool.

The output-ripple calculation assumes the primary ripple is caused by triangular inductor current charging and discharging the output capacitor. It omits capacitor equivalent series inductance, distributed PCB impedance, load dynamics, switch-node coupling, and control-loop modulation. ESR and capacitance are treated as constant at the selected operating point. These assumptions are suitable for comparing first-pass component choices, but measured ripple can differ substantially.

Limitations of this steady-state buck model

This is a first-order power-stage model. It does not calculate loop compensation, transient response, switch-node ringing, thermal rise, gate-drive loss, MOSFET output-capacitance loss, diode reverse recovery, inductor core loss or winding AC resistance. Constant switching frequency and approximately constant component values are assumed.

Real inductors lose inductance under bias, class II ceramic capacitors lose capacitance under DC voltage, and ESR changes with temperature and frequency. Enter effective operating values whenever data-sheet curves are available. Treat the waveform and ripple calculation as design guidance, then verify the chosen controller and components with simulation, tolerance analysis and bench measurements.

The generated waveform is explanatory rather than a time-domain circuit simulation. It shows a triangular current shape based on the selected mode and calculated intervals. It does not display switch-node voltage, capacitor current, current-limit clipping, subharmonic behavior, control-loop corrections, ringing, or switching transitions. The load sweep likewise recalculates a simplified steady-state point instead of simulating a changing load over time.

Thermal behavior deserves separate analysis. Semiconductor losses must be translated into junction temperature using package, PCB, airflow, copper-area, and ambient conditions. Inductor and capacitor temperatures also affect reliability and electrical values. A design that satisfies voltage and current ratings at room temperature may fail after self-heating. Use manufacturer thermal data, realistic board models, and direct temperature measurements on prototypes.

Safety, isolation, electromagnetic compatibility, surge protection, creepage, clearance, and regulatory requirements are outside the scope of this calculator. Although a low-voltage buck stage is non-isolated, its source may be connected to hazardous energy. Follow the applicable standards and use qualified engineering review for products involving mains supplies, batteries with high fault current, medical equipment, vehicles, or other safety-critical systems.

Buck converter design questions engineers ask most

Why must output voltage be below input voltage?

A buck converter only steps down. Practical drops require additional headroom, so the calculator rejects operating points that would need a duty cycle at or above 100%. Near dropout, real controllers also need enough off-time to operate their gate driver and current-sensing circuitry.

How is CCM or DCM selected?

The load is compared with half the CCM peak-to-peak ripple. When the predicted valley reaches zero, the calculator changes to its load-dependent DCM equations. An actual controller may instead force CCM, block reverse current, skip pulses, or enter burst operation.

Why can ESR ripple dominate?

Ripple current creates an immediate voltage change across ESR. A large electrolytic capacitor can therefore have a tiny ideal capacitive term but a much larger ESR term. Effective ESR at switching frequency is more useful than a low-frequency or maximum data-sheet figure.

What ripple-current target should I use?

Twenty to forty percent of maximum load is a useful starting range. Controller requirements, transient goals, losses, size and cost may justify a different target. Recalculate with inductance tolerance and DC-bias loss before finalizing the part.

Can efficiency and voltage drops be used together?

They may be entered for comparison, but they should not be compounded because both represent overlapping losses. The explicit drops support volt-second and ripple calculations, while efficiency provides a separate broad comparison.

Should maximum or minimum input voltage be entered?

Both should be checked. Maximum input commonly produces higher ripple and shorter on-time, while minimum input requires higher duty cycle and tests dropout margin. Use the actual tolerated source range rather than only its nominal value.

Does the calculated peak current equal the required current limit?

No. It is the normal steady-state peak for the entered operating point. Current-limit tolerance, startup, transients, saturation, faults, and control behavior require additional margin and controller-specific analysis.

Sources for the buck converter equations

The CCM/DCM treatment follows Erickson and Maksimović, Fundamentals of Power Electronics. Ripple, component-selection and diode equations follow Texas Instruments application report SLVA477B, Basic Calculation of a Buck Converter’s Power Stage. Preferred-value rounding uses the E12 series described by IEC 60063:2015. These references support first-pass calculations; the selected controller’s data sheet remains authoritative for limits and implementation details.

Buck converter power-stage inputs

Input voltage V_in (V)Use maximum input when checking worst-case ripple and peak current.

Output voltage V_out (V)The regulated output must be lower than the input.

Output current I_out (A)DC load current at the operating point being analyzed.

Inductance LInductance unit

Switching frequency f_swFrequency unit

Output capacitance C_out (optional)Capacitance unit

Capacitor ESR (mΩ, optional)Use ESR at the switching frequency when available.

Diode forward drop V_D (V, optional)For a synchronous buck, enter an approximate low-side FET drop.

Switch conduction drop V_SW (V, optional)Approximate high-side switch drop at the selected load.

Efficiency η (%, optional)Used only for a separate efficiency-based duty-cycle comparison.

Enter converter parameters and select Calculate power stage.

The calculated load sweep will appear here.

The calculated inductor-current waveform will appear here.

Arcade mini-game: buck converter calibration run

Catch sound design assumptions and avoid common power-stage mistakes.

Score: 0Timer: 30sBest: 0

Start the game, then use your pointer or arrow keys to catch useful inputs and avoid bad assumptions.

Buck Converter Calculator

Introduction to buck converter power-stage calculations

Formulas for buck duty cycle, ripple and conduction mode

Peak current and the CCM/DCM boundary

Capacitance and ESR contributions to output ripple

How to use this buck converter calculator

Worked example: a 12 V to 3.3 V rail at 2 A

Interpreting buck converter results and component ratings

Practical buck converter checks beyond the calculator

Assumptions behind these buck converter estimates

Limitations of this steady-state buck model

Buck converter design questions engineers ask most

Sources for the buck converter equations

Buck converter power-stage inputs

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