ADC Quantization Noise Calculator

Introduction to ADC quantization noise and ideal resolution

An analog-to-digital converter assigns each input sample to one of a finite number of codes. The difference between the continuous input and the selected code is quantization error. When a signal exercises many codes and is not coherently locked to the sampling clock, that error can be treated as approximately uniform noise. This calculator turns that model into useful engineering results: LSB voltage, RMS quantization noise, ideal signal-to-noise ratio, oversampling process gain, required bit depth and effective number of bits.

Nominal resolution describes how many codes the converter can emit; it does not guarantee that every bit contains useful information. The ideal full-scale-sine relationship is $\mathrm{SNR}=6.02N+1.76$ dB. A measured converter usually falls below this ceiling because its reference, input driver, clock and internal circuitry add noise or distortion. ENOB expresses the measured performance as the resolution of an equivalent ideal converter.

Oversampling can improve in-band performance because quantization noise is spread across the Nyquist band. Sampling faster and then applying a suitable digital low-pass and decimation filter removes out-of-band noise. This benefit is real only when the error is sufficiently noise-like and the required filter is actually implemented. The calculator therefore treats oversampling as an ideal process gain rather than a promise that any converter will gain resolution merely because its sample clock is faster.

Use the calculated values as a benchmark for architecture decisions and noise-budget work. They help answer whether a proposed bit depth is theoretically adequate, how small one code is at a chosen voltage range, and how far a measured SINAD result sits below the ideal converter limit. Final component selection should still rely on the ADC data sheet and measurements made at the intended input frequency, sample rate, reference voltage, temperature and digital-filter setting.

How to use the ADC noise, SNR and ENOB modes

Select the quantity you already know. In bit-depth mode, enter the whole-number nominal resolution $N$. The output includes the code width $q/\sqrt{12}$ and ideal SNR. Target-SNR mode solves for the minimum resolution and rounds upward to a purchasable whole bit depth. SINAD mode converts a measured sine-test result into ENOB and corrects for a tone below full scale.

Full-scale range means the entire input span. A ±5 V input therefore has a 10 V range, while a 0 V to 3.3 V input has a 3.3 V range. Do not enter only the positive half of a bipolar range. The oversampling ratio is $\mathrm{OSR}=\frac{f_s}{2\mathrm{BW}}$, where $f_s$ is the sampling rate and $\mathrm{BW}$ is the retained one-sided bandwidth. Use an OSR of 1 when the complete Nyquist band is retained.

In target-SNR mode, the requested SNR is interpreted as the desired in-band value after filtering. The calculator first subtracts ideal oversampling process gain, converts the remaining requirement into an exact number of bits and then rounds upward. The exact figure is a design threshold, not a claim that fractional physical ADC bits exist. A real converter may require a higher nominal resolution because its measured ENOB is lower than its advertised bit count.

In measured-SINAD mode, enter the SINAD from an FFT or a trustworthy data-sheet test. Enter the carrier amplitude in dBFS, with 0 dBFS representing the full-scale reference sine and backed-off signals represented by negative values. Keep the manufacturer’s amplitude convention in mind: some data sheets define a practical full-scale test tone slightly below clipping. The correction used here is mathematically valid when the entered dBFS value and measured SINAD use consistent amplitude references.

After computing, review the result summary, metric cards and nearby-bit sensitivity table. The table is particularly useful because each extra bit halves the LSB and the RMS quantization-noise voltage while improving ideal SNR by about 6.02 dB. The plot shows the corresponding staircase representation. At high resolutions the steps become too fine to see at normal screen size, but the numerical calculations retain their precision.

Formulas for LSB size, RMS quantization noise and ideal SNR

An $n$-bit ADC divides its full-scale range into $2^n$ equal code bins. Its LSB voltage is therefore:

Here $V_{\text{FS}}$ is the total full-scale range. If the error $e$ is uniform from minus half an LSB to plus half an LSB, its mean is zero and its variance is:

Taking the square root gives the familiar RMS quantization-noise voltage:

The model assumes error distributed between $-\frac{\Delta V}{2}$ and $\frac{\Delta V}{2}$. The signal used for the standard ideal-SNR calculation is a sine wave whose peak-to-peak amplitude fills the converter range. Its RMS voltage is:

Dividing signal RMS by noise RMS and expressing the amplitude ratio in decibels gives:

The LSB voltage cancels. Consequently, ideal SNR depends on bit count rather than input range. The exact constants are $20{\log }_{10}\left(2\right)N=6.0206N$ and $20{\log }_{10}\sqrt{3/2}=10{\log }_{10}(3/2)=1.7609$ dB, conventionally written as:

This is a full-scale-sine result integrated from DC to $f_s/2$. A smaller test tone has a correspondingly lower uncorrected SNR. The formula also presumes an ideal transfer function with no missing codes, offset error, gain error or transition-level irregularity. Those static errors are characterized separately and can be important even when broadband noise is low.

ADC code mapping, endpoints and the meaning of one LSB

ADC code mapping explains why apparently simple LSB calculations can differ by one code in documentation. For an ideal unipolar converter with lower endpoint V_min, a conceptual straight-binary code can be written as a clipped floor operation:

The exact transition convention is implementation-specific. Some explanations associate a code with the lower edge of its bin, while others associate it with the bin center. A useful reconstruction-level model places the represented voltage halfway through the selected interval:

The largest digital output is one less than the number of available codes:

This endpoint detail does not change the calculator’s standard engineering definition of LSB as full-scale range divided by the number of codes. It does explain why the highest ideal code value may be shown as one LSB below the upper endpoint in a code-to-voltage conversion. Data sheets may also use “LSB” to normalize offset, gain, differential nonlinearity and integral nonlinearity. In those specifications, one LSB still refers to the nominal code width, not to the measured noise floor.

The instantaneous quantization error is the difference between the input and its represented level:

Calling that error “noise” is a statistical approximation. It works well for many changing signals, especially when natural circuit noise or intentional dither prevents repeated samples from landing in the same pattern. It works poorly for a quiet DC level, a tiny periodic signal, or a coherent sine whose frequency has a simple relationship with the sampling rate. In those cases, quantization error can produce repeatable tones rather than a smooth white spectrum.

Bipolar ADCs may use offset binary or two’s-complement output coding. Coding changes the numerical interpretation of the bits but not the number of bins, LSB weight or ideal quantization-noise magnitude. Always separate input range from output representation: a ±2.5 V input range spans 5 V whether zero input appears as midscale offset binary or as a signed two’s-complement zero code.

Oversampling process gain inside the retained bandwidth

For a flat quantizer, filtering to a fraction of the Nyquist band improves the in-band result according to:

The gain uses ten times the logarithm because it represents a noise-power ratio. Each doubling adds $10{\log }_{10}2=3.01$ dB, or half a bit. An oversampling factor of four adds one bit; gaining $\beta$ bits requires an idealized factor of $4^{\beta }$. Ordinary oversampling should not be confused with sigma-delta noise shaping, which can move noise out of band more aggressively.

Process gain is obtained only after the unwanted frequency region is rejected. Merely collecting more samples without filtering or averaging does not reduce the noise contained in the original signal band. A decimation filter must have enough stop-band attenuation to prevent discarded noise and interferers from aliasing into the output band. Its transition band also consumes spectrum, so a practical filter often needs a sample rate higher than the simple theoretical minimum.

Bandwidth must be defined consistently. This calculator uses a one-sided bandwidth extending from DC to the highest retained positive frequency. For a low-pass signal, the familiar Nyquist bandwidth is half the sample rate. Band-pass systems and complex I/Q sampling use different bandwidth conventions, so their process-gain analysis should be mapped carefully before an OSR is entered.

Choosing sample rate and output bandwidth from an ADC OSR

The ADC oversampling ratio connects converter sample rate to the final retained bandwidth. Restating the definition makes the bandwidth dependence explicit:

If a target bandwidth and OSR are known, the required ideal sample rate follows directly:

For example, retaining 20 kHz with an OSR of 32 requires at least 1.28 MSPS under this definition. A practical design may sample faster to provide transition width for the analog anti-alias filter and digital decimator. The ADC’s stated maximum sampling rate is not automatically the best operating point; dynamic specifications can vary with sample rate, power mode and input frequency.

After decimation by an integer factor D, the output sample rate is:

Decimation ratio and OSR are related but are not always identical. A design might retain extra output bandwidth, use a non-integer sample-rate conversion stage, or place the passband away from DC. Multistage decimation is common because it reduces computation while maintaining strong alias rejection. Cascaded-integrator-comb filters, half-band filters and general finite-impulse-response filters each trade passband droop, latency, coefficient storage and stop-band attenuation.

Oversampling also increases raw data traffic and processing load. A 16-bit converter at 10 MSPS produces at least 160 Mbit/s before framing or multiple channels are considered. The expected process gain should therefore be balanced against interface bandwidth, memory use, FPGA resources, processor load, filter latency and power. If analog noise already dominates, a large OSR can increase system cost without producing the ideal improvement predicted from quantization noise alone.

SINAD-based ENOB and related converter specifications

SNR generally excludes harmonic distortion, while SINAD includes noise and distortion. THD measures harmonics, and SFDR compares the fundamental with the largest spur. ENOB must be derived from SINAD when it is intended to represent total usable resolution:

For a test tone below full scale, the amplitude correction is:

Because the input field uses dBFS, the correction is simply the negative of the entered tone level. For example, a −6 dBFS tone receives a +6 dB correction. dBFS is referenced to converter full scale, dBc is referenced to the applied carrier, and dBm is absolute power relative to 1 mW in a stated impedance; they are not interchangeable.

ENOB is conditional, not a universal property of a part number. It can change with input frequency because aperture jitter, track-and-hold bandwidth and distortion become more important at higher frequencies. It can also change with sample rate, input common-mode level, reference drive, supply voltage and temperature. When comparing converters, verify that SINAD was measured over a similar frequency span with similar FFT exclusions and harmonic treatment.

An FFT data sheet may list SNR, SNRFS, SINAD, THD and SFDR together. SNRFS adjusts the signal result to a full-scale reference, while ordinary SNR may use the actual carrier amplitude. SINAD normally includes harmonics in addition to integrated noise, but exact bin exclusions vary. ENOB calculated from a manufacturer’s stated SINAD should match the manufacturer only when both calculations use the same full-scale convention and frequency range.

Tone backoff and full-scale reference conventions

A backed-off ADC test tone uses less of the available range, so its RMS signal voltage is lower even though the converter’s quantization step remains unchanged. If the tone level is L dBFS relative to the full-scale sine, its RMS voltage is:

For an otherwise ideal converter, the uncorrected quantization-limited SNR falls by the same magnitude as the negative tone level:

Thus, a −1 dBFS sine has an ideal measured SNR 1 dB below the full-scale-sine result. The ENOB correction restores the full-scale reference before converting SINAD to equivalent bits. This does not erase physical noise or distortion; it only prevents ordinary amplitude backoff from being mistaken for lost converter resolution.

Real tests rarely drive exactly to the clipping threshold. A small backoff avoids overload caused by source amplitude tolerance, ADC gain error and waveform crest uncertainty. Data sheets often use −0.5 dBFS or −1 dBFS. Enter that actual level rather than assuming 0 dBFS. Also confirm whether “full scale” refers to a differential peak-to-peak input, a single-ended span, or an internally scaled digital reference.

Waveform shape matters as well. The 1.76 dB constant belongs to a sine wave. A square wave, multitone signal, noise-like waveform or modulated carrier has a different crest factor and RMS value for the same peak limit. The calculator is therefore appropriate for conventional sine-test SNR and SINAD analysis, but a communication waveform’s usable dynamic range should be evaluated from its own peak-to-average ratio and error-vector requirements.

Building a practical ADC input-referred noise budget

A practical ADC channel contains more noise than the quantizer alone. The sensor, source resistance, input amplifier, anti-alias filter, voltage reference, ADC core and power system can each contribute. When sources are statistically independent and are all referred to the same point over the same bandwidth, their RMS voltages combine by root-sum-square:

If the system has a maximum permitted total RMS noise and all contributions except the ADC are known, the remaining ADC allowance is:

This square-root subtraction is meaningful only when the specified limit exceeds the existing noise. If the other circuitry already consumes the entire budget, no ideal ADC resolution can repair the design. Reducing amplifier noise, source resistance, bandwidth or reference noise may be more effective than selecting additional nominal converter bits.

Refer each contribution through the relevant gain. Noise produced before an amplifier is multiplied by signal-path gain; noise produced after that stage is not. For a programmable-gain input, repeat the budget for each gain setting because both signal range and input-referred ADC noise can change. Differential and single-ended noise figures must also use consistent voltage definitions.

Bandwidth is essential. A noise density specified in nV/√Hz cannot be compared directly with the calculator’s RMS voltage until it is integrated through the actual analog and digital transfer functions. A simple brick-wall approximation multiplies a flat density by the square root of bandwidth, but real filters have an equivalent noise bandwidth that differs from their −3 dB cutoff. Wideband amplifier noise can also alias into the sampled band unless the anti-alias filter suppresses it.

Reference noise may be attenuated or amplified according to ADC architecture and input code. Reference buffers must also settle the converter’s switched-capacitor charge demands. Supply noise can modulate the reference, clock or comparator thresholds. These effects are not represented by the ideal quantization formula, yet they often explain why increasing nominal resolution does not improve measured system noise.

Thermal noise, spectral density and bandwidth

Thermal noise places a physical floor beneath the quantization model. For a resistor R at absolute temperature T, the open-circuit RMS noise over an ideal bandwidth B is:

Here k is Boltzmann’s constant. The square-root dependence means that reducing bandwidth by a factor of four halves the integrated RMS thermal noise. This is one reason oversampling followed by filtering can improve a noise result even when quantization noise is not the only source, although the improvement follows the actual spectrum rather than an automatic 3.01 dB per doubling.

For a frequency-dependent input-referred noise density and filter response, the more general integration is:

This expression highlights why a single bandwidth number can be insufficient. Flicker noise rises at low frequencies, amplifier voltage and current noise interact with source impedance, and filter response may contain peaking. Sampling also replicates spectra around multiples of the sample rate. Unless analog filtering is adequate, noise above the first Nyquist zone can fold into the final band and defeat a simple in-band estimate.

Compare the calculated quantization-noise voltage with integrated analog noise at the ADC input. A commonly used design approach allows analog noise to be somewhat larger than one LSB so that code transitions are naturally dithered, but the best ratio depends on the application. Precision DC measurement, audio conversion, control loops and communications receivers place different value on noise, monotonicity, latency, spur behavior and instantaneous code stability.

Clock jitter limits at higher ADC input frequencies

Sampling-clock uncertainty converts input slew rate into voltage error. For a sine wave of frequency f_in and RMS aperture jitter t_j, the approximate jitter-limited signal-to-noise ratio is:

Solving for the maximum RMS jitter associated with a desired SNR gives:

Jitter therefore becomes much more demanding as analog input frequency rises. A converter can show excellent low-frequency ENOB yet lose dynamic performance near the upper end of its input bandwidth. The relevant jitter includes the external clock source, clock distribution, ADC aperture uncertainty and any other uncorrelated timing contributions. Their RMS values are generally combined by root-sum-square.

Clock phase-noise integration must use the offset-frequency range that contributes to the measurement. Spurs may create discrete sidebands rather than a smooth noise floor, and a PLL can trade close-in against far-out phase noise. Clock amplitude and edge slew also matter because threshold noise is converted to timing uncertainty. Good clock layout, controlled impedance, clean supplies and suitable receiver levels are therefore part of the ADC noise design.

The calculator does not include jitter in its numerical output because no input frequency or jitter field is requested. If the quantization-limited SNR is higher than the jitter limit, use the lower practical ceiling and combine independent noise mechanisms in power terms. Oversampling cannot automatically recover performance lost to correlated clock spurs or distortion.

Dither, correlated quantization error and averaging

Dither is deliberate or naturally occurring noise that randomizes quantizer transitions. It can turn deterministic patterns and idle tones into a smoother spectrum, improve the average estimate of a slowly changing signal and make the q²/12 model more representative. Dither does not create information for free: it raises instantaneous noise and relies on filtering or averaging to recover a more precise mean.

For independent RMS noise contributions, including quantization noise and dither, the combined value is:

Averaging M independent samples reduces the standard deviation of white noise in the mean according to:

This square-root improvement is closely related to ordinary oversampling process gain, but independence is essential. Repeating the same deterministic quantization error does not make it disappear. Likewise, low-frequency drift, flicker noise, periodic interference and reference modulation do not necessarily average down as white noise. Allan deviation, long-term stability tests or application-specific filtering may be needed for slow precision measurements.

Too little dither may leave missing transition information in a quiet signal, while too much wastes dynamic range. Natural front-end noise is often sufficient, so intentional dither should be added only after examining code histograms or spectra. For a DC histogram test, enough samples must be collected to estimate code probabilities, and the input should remain stable relative to the noise being measured.

Sigma-delta converters use feedback and noise shaping rather than simple flat quantization noise. Their output data rate, digital filter, modulator order and decimation mode determine the in-band result. A data-sheet RMS noise table for the exact output rate and gain is usually more reliable than applying the ordinary OSR formula to the nominal modulator resolution.

Input-driver settling and acquisition-time effects

Many SAR ADCs present a switched-capacitor load to the source. During acquisition, the driver must charge the sampling capacitor close enough to the new input value. A simple first-order settling error after acquisition time t_acq is:

This model is simplified, but it shows why source impedance, acquisition time and sampling rate are linked. If settling error is comparable with an LSB, nominal resolution cannot be realized even when random noise is very low. The driver may also need to recover from charge kickback at each conversion edge, and its distortion can worsen when asked to drive a large capacitive load directly.

An RC network between amplifier and ADC can isolate kickback and provide local charge, but excessive resistance slows settling and excessive capacitance can destabilize the amplifier. Component values should follow the converter and amplifier manufacturers’ guidance, then be checked with transient simulation and hardware measurements. Multiplexed systems are more demanding because adjacent channels may produce nearly full-scale input steps.

Reference inputs can have similar dynamic behavior. A reference with low broadband noise may still perform poorly if its buffer cannot replenish conversion charge. Decoupling placement, capacitor dielectric, reference output impedance and conversion timing can all influence code noise and distortion. These implementation limits are separate from ideal quantization noise and explain why a complete ADC design cannot be selected from resolution alone.

Worked example: 12-bit ADC over a 5 V range

Consider a 12-bit ADC with a 5 V full-scale range, sampled at 1.28 MSPS and filtered to a 10 kHz bandwidth. Its OSR is $1.28\times {10}^6/(2\times 10000)=64$.

The LSB is $q=5.000/2^{12}=5.000/4096=1.2207$ mV. Its RMS quantization noise is $1.2207\text{ mV}/\sqrt{12}=352.4$ µV. The full-scale sine is $(5.000/2)/\sqrt{2}=1.7678$ V RMS, producing $20{\log }_{10}(1.7678/352.4\text{µV})=74.01$ dB, matching $6.02\times 12+1.76$.

An OSR of 64 contributes $10{\log }_{10}\left(64\right)=18.06$ dB, so the ideal in-band result is $74.01+18.06=92.07$ dB, equivalent to $(92.07-1.76)/6.02=15.00$ bits. This agrees with the fact that 64 equals $4^3$.

If a real FFT test reports 70.1 dB SINAD at −0.5 dBFS, corrected ENOB is $(70.1-1.76+0.5)/6.02=11.43$ bits. The difference from 12 nominal bits represents the combined effect of noise and distortion.

The 18.06 dB oversampling improvement is an ideal quantization-only prediction. If the input amplifier contributes broadband noise equivalent to several LSBs, or if the digital filter does not reject most out-of-band noise, measured improvement will be smaller. Conversely, a sigma-delta architecture may obtain more benefit through intentional noise shaping, but its result must be evaluated with the manufacturer’s digital-filter bandwidth and output-data-rate definitions.

Reading ADC quantization results in a system design

Compare the calculated RMS quantization noise with the input-referred noise of the reference, amplifier and sensor. If another source is already much larger, adding nominal bits will not materially improve the system. The in-band SNR is useful only if the assumed decimation filter and bandwidth match the implementation. Allow margin rather than selecting a converter whose ideal result merely equals the requirement.

The live scenario table shown after calculation compares nearby bit depths at the selected range and OSR. The waveform plot illustrates the same idea visually: increasing resolution reduces the staircase height and moves the digital representation closer to the original sine wave.

For DC measurement, translate the voltage noise into the engineering unit being sensed. If a bridge sensor produces 2 mV/V at full load and is excited from 5 V, its complete output may be only 10 mV. A 5 V ADC range would then use a small fraction of available codes unless an instrumentation amplifier provides gain. The calculator’s full-scale range should still describe the ADC input span, while sensor sensitivity and analog gain are handled separately.

For audio and communications systems, consider crest factor and headroom. A converter may need to accommodate peaks well above the average signal, so the operational SNR is lower than the full-scale-sine benchmark. Harmonic distortion, intermodulation, channel crosstalk and spurious-free dynamic range may matter more than integrated quantization noise. ENOB is helpful as a compact comparison, but it cannot describe every spectral defect.

For control systems, latency and deterministic response can outweigh the last fraction of a bit. Heavy oversampling and long digital filters improve noise while delaying feedback. For multiplexed acquisition, channel switching and settling may determine the usable sample rate. The correct converter is therefore the one that meets resolution, bandwidth, latency, linearity, input-drive and environmental requirements together.

Limitations of this ideal ADC quantization model

The relation $q^2/12$ assumes error spread across $\pm q/2$. Small DC signals or coherent periodic inputs can produce correlated error and discrete spurs instead. Dither can randomize this behavior, but it adds noise.

The calculator does not predict reference noise, amplifier noise, integral or differential nonlinearity, clock jitter, settling error, clipping or interference. Oversampling gain assumes approximately white noise and a suitable filter. Sigma-delta converters use noise shaping and require their own transfer functions and data-sheet bandwidth definitions. Treat every result as an ideal benchmark, not a substitute for measured SINAD or a complete noise budget.

The calculated LSB is based on nominal full-scale range. Reference tolerance, gain error and calibration alter the actual voltage represented by a code. Offset and gain can often be calibrated, but calibration does not remove random noise, nonlinear transitions or time-varying drift. Temperature cycling, supply changes and aging may require additional margin or periodic recalibration.

The displayed in-band equivalent bits can exceed nominal resolution under the white-noise oversampling model. That number describes reduced RMS uncertainty in a limited bandwidth; it does not increase the number of instantaneous output codes or guarantee corresponding absolute accuracy. Resolution, precision, linearity and accuracy are related but distinct properties.

Finally, numerical results are only as meaningful as the entered conventions. Confirm that full-scale voltage is the total span, SINAD and tone level refer to the same FFT measurement, OSR uses the retained one-sided bandwidth, and voltage noise is referred to the ADC input. When uncertainty remains, compare the calculator with a data-sheet example and verify the complete signal chain on hardware.